Design Examples

Design examples offer innovative ideas for Actel FPGA applications and help users create designs that utilize the many advantages of Actel's devices. Actel's design examples are available for immediate download and are always free of charge.

	AC176: Implementing Multi-Port Memories in ProASICPLUS Devices App Note  Source Code (ZIP, 10 KB, 07/04)		187 KB	7/2003	Click on the to rate this document
	AC177: Implementing Multi-Port Memories in Axcelerator Devices App Note  Source Code (ZIP, 12 KB, 07/04)		191 KB	7/2003	Click on the to rate this document
	AC210: Laser Range Finder Using Actel’s Axcelerator FPGA App Note  Design File (ZIP, 345 KB, 07/04)		1.5 MB	7/2004	Click on the to rate this document
	AC211: 32-Channel Waveform Generator Implemented Using Actel's Axcelerator FPGA App Note  Design File (ZIP, 1.2 MB, 07/04)		657 KB	7/2004	Click on the to rate this document
	AC212: Designing a SuperClock with an Axcelerator Device App Note  Design File (ZIP, 130 KB, 09/04)		419 KB	9/2004	Click on the to rate this document
	AC214: Embedded SRAM Initialization Using External Serial EEPROM App Note  Design Files (ZIP, 14.5 KB, 1/05)		396 KB	11/2008	Click on the to rate this document
	AC223: Designing a MIL-STD-1553 System Using Core1553 and Core8051 App Note  VHDL: Design Files - SFR (ZIP, 6 KB, 1/05) Design Files - direct memory access (ZIP, 13 KB, 4/05) Verilog: Design Files - SFR (ZIP, 6 KB, 1/05) Design Files - direct memory access (ZIP, 11 KB, 4/05)		147 KB	4/2005	Click on the to rate this document
	AC227: How To Use UJTAG App Note  Design Files - UJTAG (ZIP, 207 KB)		154 KB	7/2005	Click on the to rate this document
	AC230: Device Serialization for ProASICPLUS Devices App Note  Design Files (ZIP, 203 KB, 8/05)		110 KB	8/2005	Click on the to rate this document
	AC231: Frequency Fine Tuning and Clock Dithering Using Actel FPGA Devices App Note  Verilog Design Files (ZIP, 9 KB, 08/05) VHDL Design Files (ZIP, 9 KB, 08/05)		204 KB	8/2005	Click on the to rate this document
	AC245: Improving Fusion ADC Throughput App Note  Design Files (ZIP, 3.4 MB, 09/08)		951 KB	9/2008	Click on the to rate this document
	AC247: Macro Constraint Usage in ProASICPLUS Design Flow App Note  Design Files (ZIP, 270 KB)		468 KB	1/2006	Click on the to rate this document
	AC267: Context Save and Reload App Note  Design Files (ZIP, 5.4 KB, 06/06)		1.0 MB	6/2006	Click on the to rate this document
	AC271: Real-Time Calendar Applications in Actel Fusion Devices App Note  Design Files (ZIP, 3.2 MB, 06/06)		474 KB	6/2006	Click on the to rate this document
	AC273: Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs App Note – Applies to EDAC Core from Libero IDE v7.1 and Older EDAC Core from Libero IDE v7.1 or Earlier (ZIP, 41KB, 07/04)		263 KB	7/2006	Click on the to rate this document
	AC284: Configuring CorePWM Using RTL Blocks App Note  Verilog Design Files (ZIP, 2 KB, 09/06) VHDL Design Files (ZIP, 2 KB, 09/06)		204 KB	9/2006	Click on the to rate this document
	AC285: Fusion Power Sequencing and Ramp-Rate Control App Note  Design Files (ZIP, 3.1 MB, 09/06)		561 KB	9/2006	Click on the to rate this document
	AC298: Multi-Channel Analog Voltage Comparator in Fusion FPGAs  VHDL Design Files (ZIP, 3.2 MB, 01/07) Verilog Design Files (ZIP, 1.5 MB, 01/07)		176 KB	1/2007	Click on the to rate this document
	AC304: Simulating SEU Events in EDAC RAM App Note  Design File (ZIP, 582 KB, 08/07)		1.8 MB	8/2007	Click on the to rate this document
	AC305: Implementation of the SpaceWire Clock Recovery Logic in Actel RTAX-S Devices App Note  Design File (ZIP, 86 KB, 08/07) Timing Analysis (XLS, 73 KB, 08/07)		360 KB	8/2007	Click on the to rate this document
	AC307: Configuring SRAM FPGAs Using Actel Fusion App Note  SPI SRAM Configuration Design Files (ZIP, 6.4 MB, 09/07) Fusion Master Serial Design Files (ZIP, 1.5 MB, 09/07)		348 KB	9/2007	Click on the to rate this document
	AC317: Programming External Flash Memory on CoreMP7-based Development Boards App Note  Design File (ZIP, 2.4 MB, 01/08)		232 KB	1/2008	Click on the to rate this document
	AC319: Using EDAC RAM for RadTolerant RTAX-S/SL FPGAs and Axcelerator FPGAs App Note – Applies to EDAC Core from Libero IDE v7.2 and Newer EDAC Core from Libero IDE v7.2 (ZIP, 45 KB, 06/06)		707 KB	2/2008	Click on the to rate this document
	AC321: Using Fusion for Closed-Loop Power Supply Margining App Note  Libero IDE Design Files (ZIP, 14.5 MB, 05/08) Ripple Calculator (ZIP, 174 KB, 05/08)		1.2 MB	5/2008	Click on the to rate this document
	Actel Fusion Handbook  Design File (ZIP, 3 KB, Nov 30)		30.8 MB	12/2008	Click on the to rate this document
	Implementing a Brushless DC Motor Controller on an IGLOO FPGA App Note  Design Files (ZIP, 723 KB, 05/08)		117 KB	5/2008	Click on the to rate this document
	Implementing a Keypad Controller on an IGLOO FPGA App Note  Design Files (ZIP, 998 KB, 05/08)		67 KB	5/2008	Click on the to rate this document
	Implementing a Stepper Motor Controller on an IGLOO FPGA App Note  Design Files (ZIP, 1.3 MB, 05/08)		103 KB	5/2008	Click on the to rate this document
	Implementing a Tone Generator on an IGLOO FPGA App Note  Design Files (ZIP, 1.0 MB, 05/08)		64 KB	5/2008	Click on the to rate this document
	Implementing a White LED (WLED) Controller on an IGLOO FPGA App Note  Design Files (ZIP, 1.0 MB, 05/08)		68 KB	5/2008	Click on the to rate this document
	Implementing an LED (RGB) Controller on an IGLOO FPGA App Note  Design File (ZIP, 900 KB, 05/08)		71 KB	5/2008	Click on the to rate this document