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ProASIC3 FPGAs

The low-power, low-cost FPGA solution

The ProASIC3 families of flash FPGAs offer a breakthrough in power, price, performance, density, and features for today's most demanding high-volume applications. ProASIC3 devices support the ARM® Cortex™-M1 and ARM7™ soft processor IP cores, offering the benefits of programmability and time-to-market at costs as low as $0.99. The ProASIC3 families are based on nonvolatile flash technology and support 15,000 to 3,000,000 gates and up to 620 high-performance I/Os. In addition to supporting portable, consumer, industrial, communications and medical applications with commercial and industrial temperature devices, Actel also offers ProASIC3 FPGAs with specialized screening for automotive and military systems.

The ProASIC3 family includes:

  • ProASIC3
  • ProASIC3E
  • ProASIC3 for Automotive
  • ProASIC3 for Military
  • M1 ProASIC3
  • M1 ProASIC3E
  • M7 ProASIC3
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Product Features

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Key Features
  • Low power consumption
  • As low as $0.99 unit cost
  • Lowest total system cost
  • 1.5 V support
  • Cost-optimized, reprogrammable, and nonvolatile
  • Supports 128-bit AES decryption for device configuration
  • Single chip and live at power-up
  • 1,024 bits of user flash memory
  • Advanced I/O structure
  • Soft ARM7 core support
  • Immune to configuration loss due to atmospheric neutrons (firm errors)
  • Available in automotive (T-Grade) and military temperature grade
  • ISO/TS 16949:2002 certified
Product Table
ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000
CoreMP7 Devices               M7A3P1000
Cortex-M1 Devices         M1A3P250 M1A3P400 M1A3P600 M1A3P1000
System Gates 15,000 30,000 60,000 125,000 250,000 400,000 600,000 1,000,000
Typical Equivalent Macrocells 128 256 512 1,024 2,048 — — —
VersaTiles (D-Flip-Flop) 384 768 1,536 3,072 6,144 9,216 13,824 24,576
RAM kbits (1,024 bits) — — 18 36 36 54 108 144
4,608-Bit Blocks — — 4 8 8 12 24 32
FlashROM Bits 1,024 1,024 1,024 1,024 1,024 1,024 1,024 1,024
Secure (AES) ISP 1 — — Yes Yes Yes Yes Yes Yes
PLLs — — 1 1 1 1 1 1
VersaNet Globals2 6 6 18 18 18 18 18 18
I/O Standards Std. &
Hot Swap		 Std. &
Hot Swap		 Std.+ Std.+ Std.+/
LVDS		 Std.+/
LVDS		 Std.+/
LVDS		 Std.+/
LVDS
I/O Banks (+JTAG) 2 2 2 2 4 4 4 4
Maximum User I/Os 49 81 96 133 157 194 235 300
Speed Grades -F, Std. -F, Std.,
-1, -2		 -F, Std.,
-1, -2		 -F, Std.,
-1, -2		 -F, Std.,
-1, -2		 -F, Std.,
-1, -2		 -F, Std.,
-1, -2		 -F, Std.,
-1, -2
Temperature Grades C, I C, I C, I, T C, I, T C, I, T C, I C, I C, I, T, M
Single-Ended I/Os / Differential I/O Pairs
QN48   34            
QN68 49 49            
QN132   81 80 84 87/193      
VQ100   77 71 71 68/13      
TQ144     91 100        
PQ208       133 151/34 151/34 154/35 154/35
FG144     96 97 97/24 97/25 97/25 97/25
FG256         157/383 178/38 177/43 177/44
FG484           194/38 235/60 300/74
Notes:
  1. AES not available for Cortex-M1 ProASIC3 devices.
  2. Six chip (main) and twelve quadrant global networks are available for A3P060 and above.
  3. The M1A3P250 device does not support this package.
ProASIC3E Devices A3PE600 A3PE1500 A3PE3000
Cortex-M1 Devices   M1A3PE1500 M1A3PE3000
System Gates 600,000 1,500,000 3,000,000
VersaTiles (D-Flip-Flop) 13,824 38,400 75,264
RAM kbits (1,024 bits) 108 270 504
4,608-Bit Blocks 24 60 112
FlashROM Bits 1,024 1,024 1,024
Secure (AES) ISP Yes Yes Yes
Integrated PLL in CCCs1 6 6 6
VersaNet Globals2 18 18 18
I/O Standards Pro Pro Pro
I/O Banks (+JTAG) 8 8 8
Maximum User I/Os 270 444 620
Speed Grades -F, Std., -1, -2 -F, Std., -1, -2 -F, Std., -1, -2
Temperature Grades C, I C, I C, I
Single-Ended I/O / Differential I/O Pairs
PQ208 147/65 147/65 147/65
FG256 165/79    
FG324     221/110
FG484 270/135 280/139 341/168
FG676   444/222  
FG896     620/310
Notes:
  1. The PQ208 package has six CCCs and two PLLs.
  2. Six chip (main) and twelve quadrant global networks are available for A3P060 and above.

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