Actel

ProASIC3L FPGAs

The FPGA that balances low power, performance, and low cost

ProASIC3L FGPAs feature 40 percent lower dynamic power and 90 percent lower static power than the previous generation ProASIC3 FPGAs and orders of magnitude lower power than SRAM competitors, combining dramatically reduced power consumption with up to 350 MHz operation. The ProASIC3L family also supports the free implementation of an FPGA-optimized 32-bit ARM® Cortex™-M1 processor, allowing system designers to select the Actel flash FPGA solution that best meets their speed and power design requirements, regardless of application or volume. Combined with optimized software tools using Power-Driven Layout (PDL), this provides instant power reduction capabilities. In addition to supporting portable, consumer, industrial, communications, and medical applications with commercial and industrial temperature devices, Actel also offers ProASIC3EL FPGAs with specialized screening for military systems.

The ProASIC3L family includes:

  • ProASIC3L
  • ProASIC3EL
  • M1 ProASIC3L
  • M1 ProASIC3EL
  • ProASIC3EL for Military

Product Features

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Key Features
  • 40% dynamic power savings
  • Up to 90% static power savings
  • Single-chip, single-voltage operation and live at power-up
  • Optimized for high performance
  • Cost-optimized, reprogrammable, and nonvolatile
  • 1.2 V to 1.5 V core voltage support
  • Wide range of I/O voltage support from 1.2 V
  • Innovative Flash*Freeze technology for instantaneous switching from active to static mode
  • Free Cortex-M1 (ARM FPGA Processor) support for all devices
  • In-System Programming (ISP) with optional on-chip AES decryption
  • Immune to configuration loss due to atmospheric neutrons (firm errors)
  • Available in military temperature grade
Product Table
ProASIC3L Devices A3P250L A3P600L A3P1000L A3PE600L A3PE3000L
Cortex-M1 Devices   M1A3P600L M1A3P1000L   M1A3PE3000L
System Gates 250,000 600,000 1,000,000 600,000 3,000,000
VersaTiles (D-Flip-Flop) 6,144 13,824 24,576 13,824 75,264
RAM kbits (1,024 bits) 36 108 144 108 504
4,608-Bit Blocks 8 24 32 24 112
FlashROM Bits 1,024 1,024 1,024 1,024 1,024
Secure (AES) ISP1 Yes Yes Yes Yes Yes
Integrated PLLs in CCCs2 1 1 1 6 6
VersaNet Globals 18 18 18 18 18
I/O Standards Std.+/LVDS Std.+/LVDS Std.+/LVDS Pro Pro
I/O Banks (+JTAG) 4 4 4 8 8
Maximum User I/Os 157 235 300 270 620
Typical Static / Flash*Freeze Power (mW) at VCC=1.2 V 0.33 0.66 1.06 TBA 3.30
Speed Grades Std., -1 Std., -1 Std., -1 Std., -1 Std., -1
Temperature Grades C, I C, I C, I M C, I, M
Single-Ended I/Os / Differential I/O Pairs
VQ100 68/13        
PQ208 151/34 154/35 154/35   147/652
FG144 97/24 97/25 97/25    
FG256 157/38 177/43 177/44    
FG324         221/110
FG484   235/60 300/74 270/135 341/168
FG896         620/310
Notes:
  1. AES is not available for Cortex-M1 ProASIC3L devices.
  2. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.

Low-Power Benefits

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Flash*Freeze Mode ControlProASIC3L devices incorporate proven Flash*Freeze technology, which allows fast switching (within 1 µs) from an active to a static state. No additional components are required to switch from or to these states, thereby eliminating the need for additional I/O or clock management circuits. This capability makes dynamic power reduction possible by quickly switching the device in and out of Flash*Freeze mode during periods of inactivity. A ProASIC3L device can operate from a single voltage (1.2 V to 1.5 V core supply) and offers secure in-system programming (ISP) for valuable field programming upgrades.

The ProASIC3L family supports up to 3,000,000 system gates with advanced I/O options, user nonvolatile memory, Level 0 live at power-up (LAPU) support, and the industry's most secured AES encryption capability.

Power Pie Chart

The total power savings can add to more than 40 percent of dynamic power and 90 percent of static power compared to a traditional high performance FPGA design.

Dynamic Power Comparison of ProASIC3L vs SRAM FPGAs

ProASIC3 Family Resources

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Related Information

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